A printed circuit board (PCB) mechanically supports and electrically connects electronic components using conductive traces, pads and other features etched from electrically conductive sheets, such as copper sheets, laminated onto a non-conductive substrate. Multi-layered printed circuit boards are formed by stacking and laminating multiple such etched conductive sheet/non-conductive substrate. Conductors on different layers are interconnected with plated-through holes called vias, or microvias.
A printed circuit board includes a plurality of stacked layers, the layers made of alternating non-conductive layers and conductive layers. The non-conductive layers can be made of prepreg or base material that is part of a core structure, or simply core. Prepreg is a fibrous reinforcement material impregnated or coated with a resin binder, and consolidated and cured to an intermediate stage semi-solid product. Prepreg is used as an adhesive layer to bond discrete layers of multilayer PCB construction, where a multilayer PCB consists of alternative layers of conductors and base materials bonded together, including at least one internal conductive layer. A base material is an organic or inorganic material used to support a pattern of conductor material. A core is a metal clad base material where the base material has integral metal conductor material on one or both sides. A laminated stack can be formed by a single lamination step or multiple lamination steps. Using a single lamination step, the laminated stack is formed by stacking multiple core structures with intervening prepreg and corresponding microvias, then laminating the stack. Microvias can be formed using laser or mechanical through hole drilling. Microvias have a conductive material that lines the inside walls to form a conductive path. Using multiple lamination steps, a laminated stack build up starts with a core structure. Microvias are formed in this core structure. Foil lamination cycles are then performed for as many layers as are needed, thereby forming alternating layers of patterned conducting interconnects and non-conducting (dielectric) layers, such as prepreg, laminated together, where the patterned conducting interconnects are connected by microvias through the non-conducting layers. Microvias can be stacked and connected on top of each other where the conductive elements of the microvia are in contact in each layer of the stack. The microvias are filled with materials such as conductives (using copper plating for example or filled with a conductive filled material that hardens with temperature or in air forming a conductive path) or insulating material in the via cavity area leaving the conductive microvia areas accessible for contact during stacking for a continous conductive path from microvia to microvia in the stack. Interconnections between conductive layers with laminates in between can be done by stacking microvias. After the laminated stack is formed, vias through the entire laminated stack can be formed by drilling a hole through the laminated stack and plating the wall of the hole with conductive material, such as copper. The resulting plating interconnects the conductive layers in the laminated stack. Conductive pads are formed on the top surface and/or bottom surface of the laminated stack for interconnecting with discrete electronic components, both active and passive.
Under ideal conditions, the attachment between an electronic component and the PCB is free of stress, thereby enabling optimal interconnection. In practice however, the attachment between the electronic component and the PCB is subject to many types of stress, any one or combination of which may lead to degradation of the interconnection and eventual failure. One such stress is thermal-mechanical stress, also referred to as residual stress, due to thermal mismatch between the various materials within the PCB, and also thermal mismatch between the PCB itself and the electronic device attached to the PCB, such as silicon, GaAs or GaN devices. Thermal-mechanical stresses can be native as well as heat induced. Thermal mechanical stress is inherent when two materials have a mismatch of the materials thermal expansion coefficient, which is observed when exposed to temperature changes. Some thermal-mechanical stresses are caused by the cure cycle, where the PCB shrinks as it cools after curing, and other thermal-mechanical stresses are due to thermal mismatches between attached layers of different materials. There can be thermal mismatches at room temperature and also when the PCB is heated. Heating occurs, for example, during a common solder reflow process where the temperature is about 250-265 degrees C. or up to 380 degrees C. There is a thermal mismatch at this elevated temperature as well as a thermal mismatch as the PCB cools. As the layers cool, they shrink at different rates. These are processing related thermal-mechanical stresses. There are also thermal-mechanical stresses due to thermal mismatches when there is heating during operational use of the PCB, for example a mounted IC chip generates heat when in use. There are also environmental changes in temperature when the PCB is used in non-controlled environments, for example an automotive application may subject the PCB to outside temperatures that range from minus 40 degrees C. to 125 degrees C. This leads to long term environmental impact.
Current PCB technology is limited to fine feature pad pitches as low as 400 microns in high volume, conductive transmission line traces with widths as low as 40 microns and spaces between the such circuit features as low as 40 microns. For some electronic components, the pad sizes on PCBs are larger than the corresponding pads of the attached electronic components, interconnected by bumps attached to the pads on the electronic component. In order to assemble the smaller pad pitch electronic component to the larger pad pitch PCB, the electronic component is assembled onto an interposer or IC substrate, similar in configuration to BGA (ball grid array) IC chips and in some cases fabricated as a Wafer Level Chip Scale package. The IC substrate is used to connect the electronic component to the standard PCB structure. The IC substrate essentially functions as a redistribution layer. The IC substrate is a packaged component having pads on the top surface that have dimensions to match the bumps of the BGA electronic component, and bumps on the bottom surface that have larger pitch to match the larger pad sizes on the PCB. Between the top surface and the bottom surface of the IC substrate are multiple layers that increase the circuit feature dimensions from the top surface to the bottom surface and provide fan out interconnects from the top surface pads to the bottom surface bumps. The IC substrate allows for the electronic device an electrical pathway to optimize its functionality.
FIG. 1 illustrates a conventional configuration for interconnecting a smaller featured electronic component to a larger featured standard PCB using an IC substrate. A standard PCB 2 includes a laminated stack 4 having a plurality of stacked layers and multiple contact pads 6 on a top surface. An IC substrate 8 includes a substrate 9 made of multiple redistribution layers, multiple bumps 10 on a bottom surface coupled to the multiple contact pads 4 of the standard PCB 2, and multiple contact pads 12 on a top surface. An electronic component 14 includes multiple bumps 16 coupled to the multiple contact pads 12 of the IC substrate 8. The pad size and pad pitch on the top surface of the standard PCB 2substantially match the corresponding circuit feature sizes on the bottom surface of the IC substrate 8, and the pad size and pad pitch on the top surface of the IC substrate 8 substantially match the corresponding circuit feature sizes on the bottom surface of the electronic component 14. The circuit feature sizes of the electronic component 14 are smaller than the circuit feature sizes of the standard PCB 2.
An IC substrate is often fabricated using processing similar to PCB but with different materials and far smaller features, such as a 8 micron line/space. This process and material is very expensive. These processes and materials are more expensive to implement than PCB technologies and materials used to make a standard PCB. Additionally, use of an IC substrate as a redistribution layer adds more cost to the overall electronic package as there are now two layers of component-level interconnects, a first component-level interconnect layer between the PCB and the IC substrate and second component-level interconnect layer between the IC substrate and the electronic component. Further, using an IC substrate increases the height (overall thickness) due to the extra packaging and bumps. Also, each electronic component to be attached needs an IC substrate which reduces the density of electronic components that can be attached onto the PCB. The IC substrate is also an interposer which may negatively impacts signal integrity.